Extreme ultraviolet lithography (EUVL) is an emerging technology enabling the fabrication of integrated circuits with semiconductor devices having critical dimensions of less than 28 nanometers (nm) in width. In contrast to conventional lithographical techniques, EUVL utilizes extreme ultraviolet light to transfer a device pattern (e.g., circuit layout pattern) from a reflective mask (e.g., reticle) to a semiconductor wafer.
The reflective masks for EUVL are typically formed from a mask blank that includes a substrate, a reflective layer section that is formed of multiple reflector layers overlying the substrate, and an absorber layer overlying the reflective layer section. The reflective layer section and the absorber layer are tuned to be predominantly reflective and absorptive, respectively, of extreme ultraviolet light at a chosen EUV wavelength, which is typically about 13.5 nm.
Utilizing conventional lithography, a reflective mask is formed by mounting a mask blank on a vacuum chuck (e.g., a fixture configured to retain a mask via a vacuum) and patterning the absorber layer to expose selected areas of the underlying reflective layer section corresponding to the desired device pattern. The reflective mask is then moved to an EUVL tool for transferring the device pattern from the reflective mask to a semiconductor wafer. Because air readily absorbs extreme ultraviolet light (e.g., at a wavelength of about 13.5 nm), the EUVL process is carried out in a vacuum inside an EUVL tool to allow transmission of the extreme ultraviolet light. As such, in the EUVL tool, the reflective mask is mounted on an electrostatic chuck (e.g., a fixture configured to retain a mask via an electrostatic charge) instead of a conventional vacuum chuck because the vacuum chuck would be ineffective to retain the reflective mask when both the vacuum chuck and the reflective mask are in a vacuum.
The topography of a mask, and particularly of a reflective mask constructed for an EUVL process, is often different when mounted on a conventional vacuum chuck than when mounted on an electrostatic chuck. In particular, the substrate that is used for making the mask is polished to nanometer scale flatness and has some characteristic undulations resulting from the imperfect polished process. In addition, the multiple reflector and absorber layers formed overlying the substrate of the reflective mask (e.g., mask blank and reflective mask) produce interlaminar stresses that result in undulations and/or non-flatness of the outer surfaces of the reflective mask at the micrometer scale (e.g., >about 1 μm). When mounted on a vacuum chuck, the reflective mask is typically supported by a multi-point mount arrangement allowing the reflective mask some room to relax without fully constraining the undulations and/or non-flatness of the mask's outer surfaces. When mounted on an electrostatic chuck, the reflective mask is more constrained by a substantially flat plate and the large force produced from the electrostatic charge, thereby improving flatness (e.g., reducing non-flatness) of the outer surfaces of the reflective mask. Since the device pattern is transferred to the mask blank when the mask blank is mounted on the vacuum chuck and is less flat, and the device pattern is transferred from the reflective mask to the semiconductor wafer when the reflective mask is mounted on the electrostatic chuck and is more flat, topographical differences of the reflective mask due to different mounting arrangements ultimately results in image translational errors (also referred to herein as “intra-field errors”) of the device pattern to the semiconductor wafer. Intra-field errors can limit device scaling and reduce product yield.
Accordingly, it is desirable to provide methods for fabricating integrated circuits including patterning of masks for extreme ultraviolet lithography that ultimately reduce intra-field errors. Furthermore, other desirable features and characteristics of the present invention will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and this background.